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Do not change the clock source
once you select it. Selecting the
clock source while you set up
the count operation control will
corrupt the value in the binary
counter.
In the bank and linear address-
ing versions of the MN102
series, it was necessary to set
TM0EN and TM0LD to 0
between steps 3 and 4, to
ensure stable operation. This is
unnecessary in the high-speed
linear addressing version.
Panasonic Semiconductor Development Company
P2DIR (example)
Bit:
7
6
5
4
P2
P2
P2
P2
DIR7
DIR6
DIR5
DIR4
Setting:
0
1
1
0
To set up timer 0:
1.
Disable timer 0 counting in the timer 0 mode register (TM0MD). This step is
unnecessary immediately after a reset, since TM0MD resets to 0.
TM0MD (example)
Bit:
7
6
5
4
TM0
TM0
—
—
EN
LD
Setting:
0
0
0
0
2.
Set the divide-by ratio for timer 0. To divide B
the timer 0 base register (TM0BR). (The valid range for TM0BR is 0 to
255.)
TM0BR (example)
Bit:
7
6
5
4
TM0
TM0
TM0
TM0
BR7
BR6
BR5
BR4
Setting:
0
0
0
0
3.
Set the TM0LD bit of the TM0MD register to 1. This loads the value in the
base register to the binary counter. At the same time, select the clock source
as B
/4 by writing b'00' to TM0S[1:0].
OSC
TM0MD (example)
Bit:
7
6
5
4
TM0
TM0
—
—
EN
LD
Setting:
0
1
0
0
4.
Set TM0LD to 0 and TM0EN to 1. This starts the timer. Counting begins at
the start of the next cycle. When the binary counter reaches 0 and loads the
value x'01' from the base register, in preparation for the next count, a timer 0
underflow interrupt request is sent to the CPU.
102
Panasonic
16-Bit Timer Setup Examples
3
2
1
0
P2
P2
P2
P2
DIR3
DIR2
DIR1
DIR0
0
0
0
0
3
2
1
0
TM0
TM0
—
—
S1
S0
0
0
—
—
OSC
3
2
1
0
TM0
TM0
TM0
TM0
BR3
BR2
BR1
BR0
0
0
0
1
3
2
1
0
TM0
TM0
—
—
S1
S0
0
0
0
0
MN102H75K/F75K/85K/F85K LSI User Manual
Timers
x'00FFE2'
x'00FE20'
/4 by two, write x'01' to
x'00FE10'
x'00FE20'
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