Panasonic MN10285K User Manual page 307

To conform to the specification,
the clock signal must be
between 0 and 100 kHz. To sat-
isfy this requirement, always set
I2CCLK to x'032' or higher.
Panasonic Semiconductor Development Company
2
I2CCLK: I C Clock Control Register
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
C[9:0]: Output clock frequency select
This 10-bit field determines the SCL output. With a 12-MHz system clock,
calculate the frequency as follows:
In this case, the following settings apply:
x'032': 100 kHz
x'039': 89.6 kHz
x'041': 80 kHz
x'04C': 69.8 kHz
x'05A': 60 kHz
2
I2CBRST: I C Bus Reset Register
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
BRST: Bus reset
When a serious bus error occurs, this bit can be set to 0, forcing the clock
line low and resetting the I
After a forced reset, the microcontroller is in slave receiver mode. This reset
does not change the contents of the I2CMYAD and I2CCLK registers.
0: Force bus to reset
1: Steady state
2
I2CBSTS: I C Bus Status Register
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
I2CBSTS is a two-bit, read-only register that monitors the status of the I
bus.
SDAS: SDA data line status
This bit monitors the state of the I
SCLS: SCL clock line status
This bit monitors the state of the I
306
Panasonic
11 10 9 8 7 6
— — C9 C8 C7 C6
0 0 0 0 0 0
R R R/W R/W R/W R/W
12 MHz
f = -------------------------------------------------------------------- -
SCL
2 Register setting
x'06E': 50 kHz
x'08C': 40 kHz
x'0BE':30 kHz
x'122': 20 kHz
x'24E': 10 kHz
11 10 9 8 7 6
— — — — — —
0 0 0 0 0 0
R R R R R R
2
C bus. This function works in all I
11 10 9 8 7 6
— — — — — —
0 0 0 0 0 0
R R R R R R
2
C data line, SDA.
2
C clock line, SCL.
MN102H75K/F75K/85K/F85K LSI User Manual
2
I C Bus Controller
2
I C Bus Interface Registers
x'007E46'
5 4 3 2 1
C5 C4 C3 C2 C1
0 0 0 0 0
R/W R/W R/W R/W R/W
10
x'007E48'
5 4 3 2 1
— — — — — BRST
0 0 0 0 0
R R R R R
2
C modes.
x'007E4A'
5 4 3 2 1
— — — — SDAS SCLS
0 0 0 0 0
R R R R R
0
C0
0
R/W
0
1
R/W
0
0
R
2
C