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ROM Correction
Block Diagram
MN102H75K/F75K/85K/F85K LSI User Manual
12.2 Block Diagram
Figure 12-3 is a block diagram of the ROM correction circuit. A match detection
circuit constantly monitors the ROM address specified by the CPU instruction
pointer (IP). When the value matches a correction address, the circuit replaces the
data output from the ROM with the data in the appropriate correction data
register. It then sends the corrected data to the CPU.
Data bus
ROM
address
Correction
Correction
address
match
registers
registers
Correction
address
Match
detection
circuit
Figure 12-3 ROM Correction Block Diagram
12.3 Programming Considerations
At reset, the ROM correction address match and data registers contain all 0s.
Since a reset also disables ROM correction (in ROMCEN), the ROM will still
operate normally.
Only read from or write to the address match registers while ROM correction is
disabled in ROMCEN. Otherwise, an error may occur in the match detection circuit.
Note that the address match and data registers only allow full-register access (8-
bit or 16-bit depending on the register). You cannot write to individual bits.
289
Panasonic
data
ROM
Correction
data
MUX (selector)
IP
CPU
Panasonic Semiconductor Development Company
ROM correction
enable
registers
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