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Not using internal pullup func-
tion,Figuer10-2 connect the
external pullup registance
Panasonic Semiconductor Development Company
10.2 Block Diagram
MSB
PWM0 - PWM6
7
6
x'007E70' - x'007E7C'
f
PWM
Note: With a 4-MHz oscillator:
f
= f
PWM
SYSCLK
Output pulse cycle = 2
Minimum pulse width = 1/f
t
= (PWMn + 1) 0.67 µs
LOW
10.3 PWM Data Registers
All registers in PWM function cannot be written by byte (be word only). Read by
byte is possible.
Bits 7 to 0 of each of the seven PWM data registers (PWM0 to PWM6) hold the
8-bit pulsewidth modulated data to be written to the PWMs. The registers reset to
0, and they set to 1 when PWM output is high.
PWM0–PWM6: PWMn Data Registers
Bit:
7
6
5
4
PWMn7 PWMn6 PWMn5 PWMn4 PWMn3 PWMn2 PWMn1 PWMn0
Reset:
0
0
0
0
R/W:
R
R
R
R
250
Panasonic
Data bus
8
5
4
3
2
1
0
DAC output
PWM (8-bit)
I/O control
PnDIR
/16
8
/f
= 341.3 µs
PWM
= 1.33 µs
PWM
Figure 10-2 PWM Block Diagram
3
2
1
0
0
0
0
0
R
R
R
R
MN102H75K/F75K/85K/F85K LSI User Manual
Pulse Width Modulator
Block Diagram
PnPUP
PnCNT
PWMn
(P15 - P17,
MUX
P20 - P23)
Port
x'007E70'–x'007E7C'
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