Panasonic MN10285K User Manual page 312

H Counter
H Counter Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
HCD0: H Counter Data Register 0
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
HCD[90:00]: Count from HI0 source signal
This field stores the HI0 clock source count. It becomes x'3FF' on over-
flow.
HCD1: H Counter Data Register 1
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
HCD[91:01]: Count from HI1 source signal
This field stores the HI1 clock source count. It becomes x'3FF' on over-
flow.
311
Panasonic
11 10 9 8 7 6
HCD HCD HCD HCD
— —
90 80 70 60
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
HCD HCD HCD HCD
— —
91 81 71 61
0 0 0 0 0 0
R R R R R R
Panasonic Semiconductor Development Company
x'007EB4'
5 4 3 2 1
HCD HCD HCD HCD HCD HCD
50 40 30 20 10 00
0 0 0 0 0
R R R R R
x'007EB6'
5 4 3 2 1
HCD HCD HCD HCD HCD HCD
51 41 31 21 11 01
0 0 0 0 0
R R R R R
0
0
R
0
0
R