Panasonic MN10285K User Manual page 56

Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
TM4UDICL: Timer 4 Underflow Interrupt Control Register (Low)
Bit: 7 6 5 4
TM4UD
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
TM4UDICL detects and requests timer 4 underflow interrupts. It is an 8-
bit access register. Use the MOVB instruction to access it.
TM4UDIR: Timer 4 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM4UDID: Timer 4 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM4UDICH: Timer 4 Underflow Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
TM4UDICH enables timer 4 underflow interrupts. It is an 8-bit access regis-
ter. Use the MOVB instruction to access it.
The priority level for timer 4 underflow interrupts is written to the
TM4CBLV[2:0] field of the TM4CBICH register.
TM4UDIE: Timer 4 underflow interrupt enable flag
0: Disable
1: Enable
VBIICL: VBI (1) Interrupt Control Register (Low)
Bit: 7 6 5 4
VBI
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
VBIICL detects and requests VBI (1) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
VBIIR: VBI (1) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIID: VBI (1) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
55
Panasonic
3 2 1 0
TM4UD
— — —
ID
0 0 0 0
R R R R
3 2 1 0
TM4UD
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
VBI
— — —
ID
0 0 0 0
R R R R
Panasonic Semiconductor Development Company
x'00FC64'
x'00FC65'
x'00FC66'