Functional Description; Analog-To-Digital Converter; Recommended Adc Configuration; External Connection With Both Ccd0 And Ccd1 Unused - Panasonic MN10285K User Manual

The constants shown in figures 9-2
to 9-4 are recommended values
only. Operation at these values is
not guaranteed.
Panasonic Semiconductor Development Company
9.3

Functional Description

9.3.1

Analog-to-Digital Converter

The analog-to-digital converter (ADC) converts the clamped video signal to 8-bit
digital data using a 12-MHz sampling clock. Figure 9-2 shows an example con-
figuration using the recommended external pin connections. In this example, both
caption decoders are used. Figure 9-3 shows the recommended connection when
neither decoder is used, and figure 9-4 shows that when only CCD0 is used.
3.3 V
8.2 k
18 k
+
VIDEO IN 0
240
1 F
560 pF
1k
Low pass filter
3.3 V
8.2 k
18 k
+
VIDEO IN 1
240
1 F
560 pF
Low pass filter
Figure 9-2 Recommended ADC Configuration
CLH
(Used as P30)
VREFHS
CVBS0
(Used as P31)
CVBS1
(Used as P32)
VREFLS
CLL
(Used as P33)
Figure 9-3 External Connection with
Both CCD0 and CCD1 Unused
228

Panasonic

Closed-Caption Decoder
Power Down
VREFHS
VREFH
3.3 V
+
A/D
1 F
VREFL
+
IN
1 F
1 k
CVBS0
3.3 V
6.8 k
CLL
Clamping
circuit
CLH
33 k
CVBS1
3.3 V
IN
Power Down
+
VREFLS
VREFH
+
1 F
1 F A / D
1 k
VREFL
33 k
VIDEO IN
6.8 k
Figure 9-4 External Connection with
Only CCD1 Unused
MN102H75K/F75K/85K/F85K LSI User Manual
Functional Description
ADC0ON
(PCNT0: x'00FF90', bit 4)
ADDATA[7: 0]
OUT
VBI0OFF
(PCNT0: x'00FF90', bit 0)
CLK
ADC1ON
(PCNT0: x'00FF90', bit 5)
ADDATA[7: 0]
OUT
f
SYSCLK
(12 MHz)
CLK
VBI1OFF
(PCNT0: x'00FF90', bit 1)
CLH
VREFHS
+
1 µF
External
CVBS0
circuit
CVBS1
(Used as P32)
VREFLS
CLL