Cri Detection For Sampling Clock Generation; Data Capture Control; Sampling Clock Timing Determination; Caption Data Capture Timing - Panasonic MN10285K User Manual

Closed-Caption Decoder
Functional Description
MN102H75K/F75K/85K/F85K LSI User Manual

9.3.5.1 CRI Detection for Sampling Clock Generation

The decoder captures the caption data on the rising edge of the CRI pulse. To
achieve this, it contains a circuit to accurately detect the CRI pulse rises and to
generate a data sampling clock.
CRI
21 HSYNC
CRI2S
CRI2E
CRI detection
Figure 9-10 Sampling Clock Timing Determination

9.3.5.2 Data Capture Control

The DATAS and DATAE registers control the data capture timing, and the
CAPDATA register stores the caption data captured on the sampling clock gen-
erated through CRI detection. The HNUM register controls interrupt timing.
CRI
21 HSYNC
DATAS
(CRI2S)
Figure 9-11 Caption Data Capture Timing
235

Panasonic

Data
This interval determines the sampling clock timing.
Data
(Sampling clock)
DATAE
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