Block Diagram; Functional Description; Control Registers For Clamping Circuit; C Bus Controller Block Diagram - Panasonic MN10285K User Manual

Panasonic Semiconductor Development Company

13.2 Block Diagram

SDA
Digital
filter
Parallel-to-serial
Data bus
controller
Serial-to-parallel
SCL
Digital
filter
Clock
controller
Bus busy logic
Arbitration logic
Clock prescaler
Figure 13-4 I

13.3 Functional Description

2
The I C bus controller contains the registers shown in table 13-3. See the page
number indicated for register and bit descriptions.
Table 13-3 Control Registers for Clamping Circuit
Register Page Address
I2CDTRM x'007E40'
304
I2CDREC 305 x'007E42'
I2CMYAD x'007E44'
305
I2CCLK 306 x'007E46'
I2CBRST x'007E48'
306
I2CBSTS 306 x'007E4A'
Arbitration and bus busy control
2
The I C bus controller allows software control, but implements communication
timing and bus arbitration completely in the hardware.
Arbitration: Controlled by the software, but implemented completely
in the hardware.
Bus busy: Checked by the hardware. This eliminates the need for the
software to check whether the bus is busy. The program can request a
2
transfer to the I C bus at any time.
296

Panasonic

Bus buffer
Transmission data register
MSB
converter
Reception data register
MSB
converter
Address comparator
Address register
Clock register
Control register
Status register
MODE STS LRB
2
I C sequence controller
2

C Bus Controller Block Diagram

Description
2
I C transmission data register
2
I C reception data register
2
I C self address register
2
I C clock control register
2
I C bus reset register
2
I C bus status register
MN102H75K/F75K/85K/F85K LSI User Manual
2
I C Bus Controller
Block Diagram
D[14 :0]
LSB
LSB
STA STO ACK
AAS LAB BB
Register control