Vram Organization; Vram Organization (When Gexte = 0); Panasonic - Panasonic MN10285K User Manual

On-Screen Display
VRAM
x'008000'
Program
Data
and
Stack
Area
GRAMEND 40 N 5
Graphics
VRAM
GRAMEND
CRAMEND 50 M 1
Text
VRAM
CRAMEND
x'009FFF'
Notes: 1. All addresses are expressed in hex notation. Other values are decimal.
2. GRAMEND: Graphics RAM end address (programmable to any address)
3. CRAMEND: Text RAM end address (programmable to any address)
4. M: Number of lines in the text layer
5. m: 1 and up
6. N: Number of lines in the graphics layer
7. n: 1 and up
MN102H75K/F75K/85K/F85K LSI User Manual
7.8.2

VRAM Organization

Graphics RAM Addresses
(When GEXTE = 1)
GRAMEND 40 N 5
Line N data
GRAMEND 40 (N 1)
.
.
.
GRAMEND 40 n 5
Line n data
GRAMEND 40 (n 1)
.
.
.
GRAMEND 7B
Line 2 data
GRAMEND 40
GRAMEND 3B
Line 1 data
GRAMEND
Text RAM Addresses
CRAMEND 50 M 1
Line M data
CRAMEND 50 (M 1)
.
.
.
CRAMEND 50 m 1
Line m data
CRAMEND 50 (m 1)
.
.
.
CRAMEND 9F
Line 2 data
CRAMEND 50
CRAMEND 4F
Line 1 data
CRAMEND
Figure 7-6 VRAM Organization (When GEXTE = 0)
169

Panasonic

GRAMEND 3F
Unused area
GRAMEND 3E
GRAMEND 3D
Unused area
GRAMEND 3C
GRAMEND 3B
Code 30
GRAMEND 3A
GRAMEND 2F
Code 29
GRAMEND 2E
.
.
.
GRAMEND 3
Code 2
GRAMEND 2
64 bytes
GRAMEND 1
Code 1
GRAMEND
CRAMEND 4F
Code 40
CRAMEND 4E
CRAMEND 4D
Code 39
CRAMEND 4C
CRAMEND 4B
Code 38
CRAMEND 4A
.
.
.
CRAMEND 3
Code 2
CRAMEND 2
80 bytes
CRAMEND 1
Code 1
CRAMEND
Panasonic Semiconductor Development Company
Low-order 8 bits
of graphics code
High-order 8 bits
2 bytes
of graphics code
Low-order 8 bits
of text code
High-order 8 bits
2 bytes
of text code