Panasonic MN10285K User Manual page 58

Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
TM5CAICL: Timer 5 Compare/Capture A Interrupt Control Register (Low) x'00FC6A'
Bit: 7 6 5 4
TM5CA
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
TM5CAICL detects and requests timer 5 compare/capture interrupts. It is
an 8-bit access register. Use the MOVB instruction to access it.
TM5CAIR: Timer 5 compare/capture A interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM5CAID: Timer 5 compare/capture A interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM5CAICH: Timer 5 Compare/Capture A Interrupt Control Register (High) x'00FC6B'
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
TM5CAICH enables timer 5 compare/capture interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
The priority level for timer 5 compare/capture interrupts is written to the
TM5CBLV[2:0] field of the TM5CBICH register.
TM5CAIE: Timer 5 compare/capture A interrupt enable flag
0: Disable
1: Enable
TM5UDICL: Timer 5 Underflow Interrupt Control Register (Low)
Bit: 7 6 5 4
TM5UD
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
TM5UDICL detects and requests timer 5 underflow interrupts. It is an 8-
bit access register. Use the MOVB instruction to access it.
TM5UDIR: Timer 5 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM5UDID: Timer 5 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
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3 2 1 0
TM5CA
— — —
ID
0 0 0 0
R R R R
3 2 1 0
TM5CA
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
TM5UD
— — —
ID
0 0 0 0
R R R R
Panasonic Semiconductor Development Company
x'00FC6C'