Table of Contents
Advertisement
H Counter
Description
14 H Counter
MN102H75K/F75K/85K/F85K LSI User Manual
14.1 Description
The MN102H75K/85K contains two H counter circuits that can be used to count
the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit
register.
14.2 Block Diagram
VI0
VSYNC
PWM10
Divider
waveform
341-µs signal
from PWM block
HI0/HI1
HI0 for H counter 0, and
HI1 for H counter 1
Figure 14-1 H Counter Block Diagram
14.3 H Counter Operation
Figure 14-2 provides a schematic diagram of an example counter operation.
Note: In this example, HI0 is active high and VSYNC is active low.
Figure 14-2 H Counter Operation Example
307
Panasonic
Selected in SELR[20:00]/SELR[21:01] fields
of HCCNT0/HCCNT1 registers.
Selected in REDG0/REDG1 bits
of HCCNT0/HCCNT1 registers.
M
1024 µs
Polarity
U
2048 µs
X
4096 µs
8192 µs
Count source
Polarity
switch
Selected in SEDG0/SEDG1 bits
of HCCNT0/HCCNT1 registers.
Panasonic Semiconductor Development Company
switch
Reset
10-bit counter
Latch
10-bit register
Data bus
Advertisement
Table of Contents
