Panasonic MN10285K User Manual page 249

Panasonic Semiconductor Development Company
CLPCND1: Clamping Control Signal Status Register 1
(CLPCNDW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
This register is for monitoring the status of the clamping current source
switch shown in figure 9-5 on page 229. An N-channel transistor is on
when the associated bit (PEDOWN, XPEDOWN, CLPN, or SAFEN) is 1.
A P-channel transistor is on when the associated bit (PEDUP, XPEDUP,
CLPP, or SAFEP) is 0.
SAFEP: Low clamping control pulse for high current source (P-channel)
SAFEN: Low clamping control pulse for high current source (N-channel)
CLPP: High clamping control pulse for high current source (P-channel)
CLPN: High clamping control pulse for high current source (N-channel)
XPEDUP: Clamping control pulse for medium current source (P-channel)
XPEDOWN: Clamping control pulse for medium current source (N-channel)
PEDUP: Clamping control pulse for low current source (P-channel)
PEDOWN: Clamping control pulse for low current source (N-channel)
SBFNUM: Sampling Start Position Register
(SBFNUMW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
SBFNUM[10:0]: Detected position of start bit flag (detected by the hardware)
TESTA: Test Register
(TESTA
Bit: 15 14 13 12
SLICE SLICE SLICE SLICE SLICE
7 6 5 4
Reset: 0 0 0 0
R/W: R R R R
SLICE[7:0]: Slicing value (either from hardware calculation or software setting)
DATAG: Data window (for capturing the caption data)
CRI2G: CRI window 2 (for detecting the sampling cycle position)
CRI1G: CRI window 1 (for calculating the maximum and minimum values)
ACQG: ACQ window (for setting the H interval for data detection)
SLDSAMP: Caption data sampling pulse
FCPIN: Start position for start bit detection (software setting)
FCP: Start position for start bit detection (hardware calculation)
SLD: Sliced data from the CVBS input signal
248
Panasonic
Closed-Caption Decoder
Closed-Caption Decoder Registers
11 10 9 8 7 6
SAFE
— — — — SAFEP
N
0 0 0 0 1 0
R R R R R R
11 10 9 8 7 6
SBF SBF SBF SBF SBF
— NUM NUM NUM NUM NUM
10 9 8 7 6
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
SLICE SLICE SLICE DATA
CRI2G CRI1G ACQG
3 2 1 0 G
0 0 0 0 0 0
R R R R R R
MN102H75K/F75K/85K/F85K LSI User Manual
x'007EDC'
x'007EFC')
5 4 3 2 1
XPED XPE PED PE
CLPP CLPN
UP DOWN UP DOWN
1 0 1 0 1
R R R R R
x'007E4C'
x'007E6C')
5 4 3 2 1
SBF SBF SBF SBF SBF SBF
NUM NUM NUM NUM NUM NUM
5 4 3 2 1
0 0 0 0 0
R R R R R
x'007E4E'
x'007E6E')
5 4 3 2 1
SLD
FCPIN FCP SLD
SAMP
0 0 0 0 0
R R R R R
0
0
R
0
0
0
R
0
0
R