Backporch Position Setting; Sync Separator Level; Panasonic - Panasonic MN10285K User Manual

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Use this register to specify the position for capturing the pedestal level
value used during pedestal clamping. Specify a number of ADC clocks
after the leading edge of HSYNC. The valid range is x'000' to x'1FF', and
the recommended setting is x'003C'.
HSYNC
Pedestal level for BPLV register
Figure 9-13 Backporch Position Setting
SYNCMIN: Sync and Pedestal Level Register
(SYNCMINW
Bit: 15 14 13 12
— BPLV6 BPLV5 BPLV4 BPLV3 BPLV2 BPLV1 BPLV0
Reset: 0 0 0 0
R/W: R R R R
BPLV[6:0]: Pedestal level
This register stores the pedestal level captured from the position specified
in BPPST.
SYNCMIN[6:0]: Minimum sync level
This field stores the minimum level (the sync tip level) detected during the
interval set in the SCMING register. For sync tip clamping, you should
control clamping so as to make this value 16 (dec).
SPLV: Sync Separator Level Set Register
(SPLVW
Bit: 15 14 13 12
— — BSP5 BSP4 BSP3
Reset: 0 0 0 1
R/W: R R R/W R/W R/W
The sync separator uses the value set in this register to separate the com-
posite sync signal from the composite video signal.
HSYNC
244

Panasonic

Closed-Caption Decoder
Closed-Caption Decoder Registers
Video signal
Set this interval in BPPST
11 10 9 8 7 6
SYNC
—
MIN6
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
BSP2 BSP1 BSP0 — —
1 0 0 0 0 0
R/W R/W R/W R R
Video signal
Composite sync processing
Figure 9-14 Sync Separator Level
MN102H75K/F75K/85K/F85K LSI User Manual
x'007EC8'
x'007EE8')
5 4 3 2 1
SYNC SYNC SYNC SYNC SYNC SYNC
MIN5 MIN4 MIN3 MIN2 MIN1 MIN0
0 0 0 0 0
R R R R R
x'007ECA'
x'007EEA')
5 4 3 2 1
PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
0 1 1 0 0
R/W R/W R/W R/W R/W R/W
Setting for sync
separator level
0
0
R
0
0