Table of Contents
Advertisement
2
I
C Bus Controller
SDA and SCL Waveform Characteristics
S
P
SDA
t
BUF
t
HD
SCL
t
t
;STA
HD
LOW
MN102H75K/F75K/85K/F85K LSI User Manual
13.5 SDA and SCL Waveform Characteristics
Figure 13-6 and table 13-5 provide the timing definitions and specifications for
the for the MN102H75K/85K I
t
; DAT
; DAT
SU
t
t
t
R
HIGH
F
Figure 13-6 SDA and SCL Waveforms
Table 13-5 SDA and SCL Waveform Characteristics
SCL clock frequency
Bus free time between a stop and start condition
Hold time (repeated) start condition
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated start condition
Data hold time
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Stop condition setup time
Panasonic
2
C bus interface.
Sr
t
t
; STA
; STA
SU
HD
Parameter
Panasonic Semiconductor Development Company
299
t
; STO
SU
Symbol
Min
Max
f
0
100
SCL
t
20
—
BUF
t
4.0
—
HD;STA
t
4.7
—
LOW
t
4.0
—
HIGH
t
4.7
—
SU;STA
t
300
—
HD;DAT
t
250
—
SU;DAT
t
—
1000
R
t
—
300
F
t
4.0
SU;STO
P
Unit
kHz
µs
ns
µs
Advertisement
Table of Contents
