Panasonic MN10285K User Manual page 69

Panasonic Semiconductor Development Company
TM3UDICH: Timer 3 Underflow Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
TM3UDICH enables timer 3 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 3 underflow interrupts is written to the
VBIVLV[2:0] field of the VBIVICH register.
TM3UDIE: Timer 3 underflow interrupt enable flag
0: Disable
1: Enable
OSDGICL: OSD (Graphics) Interrupt Control Register (Low)
Bit: 7 6 5 4
OSDG
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
OSDGICL detects and requests OSD (graphics) interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
OSDGIR: OSD (graphics) interrupt request flag
0: No interrupt requested
1: Interrupt requested
OSDGID: OSD (graphics) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
OSDGICH: OSD (Graphics) Interrupt Control Register (High)
Bit: 7 6 5 4
OSDG OSDG OSDG
—
LV2 LV1 LV0
Reset: 0 0 0 0
R/W: R R/W R/W R/W
OSDGICH sets the priority level for and enables OSD (graphics) inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
OSDGLV[2:0]: OSD (graphics) interrupt priority level
Sets the priority from 0 to 6.
OSDGIE: OSD (graphics) interrupt enable flag
0: Disable
1: Enable
68
Panasonic
Interrupt Control Registers
3 2 1 0
TM3UD
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
OSDG
— — —
ID
0 0 0 0
R R R R
3 2 1 0
OSDG
— — —
IE
0 0 0 0
R R R R/W
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
x'00FC8D'
x'00FC90'
x'00FC91'