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The watchdog timer interrupt is
provided for detecting and handling
racing. Normal operation is not
guaranteed if the program returns
after a watchdog interrupt. For
actions requiring returns, use a
timer interrupt.
If WDM[1:0] = 00, a watchdog
interrupt occurs when the watch-
16
dog timer counts 2
cycles
(5.4613 ms at 4-MHz f
/12-
OSC
MHz f
). The WDM set-
SYSCLK
tings have the following mean-
ings:
16
00:
2
(5.46 ms)
4
01:
2
(1.33 µs)
12
10:
2
(0.34 ms)
14
11:
2
(1.37 ms)
The main program normally
clears the watchdog timer prior
to a watchdog interrupt.
Panasonic Semiconductor Development Company
2.2.2
Setting Up a Watchdog Timer Interrupt
In this example, a watchdog timer reset occurs. The watchdog timer starts
running after a reset, when the NWDEN flag in the CPU mode register (CPUM)
is enabled (set to 0). When the watchdog timer overflows, a nonmaskable
interrupt occurs. This means that the watchdog timer must be cleared in the main
program.
P0
P5
P2
Figure 2-6 Block Diagram of Watchdog Timer Interrupt
Enabling watchdog timer interrupts
1.
Enable interrupts by writing a 1 to the interrupt enable flag (IE) in the PSW
and setting the interrupt masking level (IM[2:0]) to 7 (b'111').
2.
Activate the watchdog timer by clearing the NWDEN bit of the CPUM regis-
ter. Set the time limit for the racing detection function in the WDM[1:0]
field.
CPUM (example)
Bit:
15
14
13
12
NW
WDM
WDM
—
DEN
1
0
Setting:
0
0
0
0
Clearing the watchdog timer
3.
Set the NWDEN bit in CPUM to 1, then immediately reset it to 0. The
watchdog timer clears to 0 when NWDEN is 1.
42
Panasonic
CORE
ROM, RAM
Interrupts
Bus Controller
Timers 0-5
Serial I/Fs
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
Interrupt Setup Examples
P1
P3
ADC
x'00FC00'
5
4
3
2
1
OSC
—
STOP HALT OSC1 OSC0
ID
0
0
0
0
0
0
0
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