Panasonic MN10285K User Manual page 248

Closed-Caption Decoder
Closed-Caption Decoder Registers
MN102H75K/F75K/85K/F85K LSI User Manual
HDISTW: Sync Separator Detection Control Register 2
HDISTWW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
HDISTW[8:0]: HSYNC count setting the interval for sync separation detection
In this register, set the interval during which sync separation occurs. The
valid range is x'000' to x'1FF' and the recommended setting is x'0100'.
For NTSC format, set the register to 525 (dec), indicating an HSYNC
count of 525 VSYNC cycles. The recommended setting is x'0100'.
VCNT: VSYNC Separator Control Register
(VCNTW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
VSEPSEL: VSYNC signal select
0: 0H to 127H VSYNC separation mask
1: No mask
VSEPLMT[2:0]: VSYNC separation detection threshold
HVCOND: Sync Separator Status Register
(HVCONDW
Bit: 7 6 5 4
— — — STPN
Reset: 0 0 0 1
R/W: R R R R
Use this register to monitor the status of the sync separator.
STPN: Status of clamping control pulse signal during STOP
COMPSY: Composite sync signal status
VSEP: VSYNC signal status
HSEP: HSYNC signal status
HLOCK: Sync detection
0: Asynchronous
1: Synchronous
247
Panasonic
11 10 9 8 7 6
HDIST HDIST HDIST
— — —
W8 W7 W6
0 0 0 1 0 0
R R R R/W R/W R/W
11 10 9 8 7 6
VSEP
— — — — —
SEL
0 0 0 0 0 0
R R R R/W R R
3 2 1 0
COMP
VSEP HSEP HLOCK
SY
1 0 0 0
R R R R
Panasonic Semiconductor Development Company
x'007ED6'
x'007EF6')
5 4 3 2 1
HDIST HDIST HDIST HDIST HDIST HDIST
W5 W4 W3 W2 W1
0 0 0 0 0
R/W R/W R/W R/W R/W R/W
x'007ED8'
x'007EF8')
5 4 3 2 1
VSEP VSEP VSEP
— — —
LMT2 LMT1 LMT0
0 0 0 1 0
R R R R/W R/W R/W
x'007EDA'
x'007EFA')
0
W0
0
0
1