Setting Up Hardware-Controlled Intermittent Three-Channel A/D Conversion; Timing Of Software-Controlled Single-Channel A/D Conversion; Multiple-Channel A/D Conversion; Panasonic - Panasonic MN10285K User Manual

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AN6BUF (example)
Bit: 15 14 13 12 11
— — — — —
ANCTR
set
ANEN
State
Reference
clock
AN6BUF
AN6BUF
read
Interrupt
Figure 6-9 Timing of Software-Controlled Single-Channel A/D Conversion
6.5.2 Setting Up Hardware-Controlled Intermittent Three-Channel
A/D Conversion
This example illustrates multiple-channel conversion controlled by the hardware.
The ADIN2, ADIN1, and ADIN0 pins input analog voltage signals ( 0.0 V– 3.3
V) and the ADC converts the voltages to 8-bit digital values. It writes the results
to the registers periodically, each time timer 1 underflows.
Slider 1 Slider 2
10
5
0
ch0
A/D converter data registers
Underflow
Timer 1
Figure 6-10 Multiple-Channel A/D Conversion
148

Panasonic

Analog-to-Digital Converter
10 9 8 7 6
ANn ANn ANn
— — —
BUF7 BUF6 BUF5
ADIN6 converting
1 2 3 4
Slider 3
10 10
5 5
0 0
ch1 ch2
MN102H75K/F75K/85K/F85K LSI User Manual
ADC Setup Examples
x'00FF14'
5 4 3 2 1 0
ANn ANn ANn ANn ANn
BUF4 BUF3 BUF2 BUF1 BUF0
10 11 12
VALID
MN102H75K
MN102
CPU core