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Timers
8-Bit Timer Setup Examples
Do not change the clock source
once you select it. Selecting the
clock source while you set up
the count operation control will
corrupt the value in the binary
counter.
MN102H75K/F75K/85K/F85K LSI User Manual
TM2UDICH (example)
Bit:
7
6
5
4
TM2UD
TM2UD
TM2UD
—
LV2
LV1
LV0
Setting:
0
1
0
0
TM2UDICL (example)
Bit:
7
6
5
4
TM2UD
—
—
—
IR
Setting:
0
0
0
0
TM1UDICH (example)
Bit:
7
6
5
4
—
—
—
—
Setting:
0
0
0
0
TM1UDICL (example)
Bit:
7
6
5
4
TM1UD
—
—
—
IR
Setting:
0
0
0
0
3.
Set the divide-by ratio for timer 0. Since the timer will count 60,000 cycles
(x'EA60'), write x'5F' to the timer 1 base register (TM1BR) and x'EA' to
the timer 2 base register (TM2BR). (The valid range for TMnBR is 0 to
255.)
TM1BR (example)
Bit:
7
6
5
4
TM1
TM1
TM1
TM1
BR7
BR6
BR5
BR4
Setting:
0
1
0
1
TM2BR (example)
Bit:
7
6
5
4
TM2
TM2
TM2
TM2
BR7
BR6
BR5
BR4
Setting:
1
1
1
0
4.
Set the TM1LD bit of the TM1MD register and theTM2LD bit of the
TM2MD register to 1. This loads the value in the base register to the binary
counter. At the same time, select the clock source as the BOSC/4 for timer 1
and cascade to timer 1 for timer 2. (Write to TMnS[1:0]).
TM1MD (example)
Bit:
7
6
5
4
TM1
TM1
—
—
EN
LD
Setting:
0
1
0
0
85
Panasonic
3
2
1
0
TM2UD
—
—
—
IE
0
0
0
1
3
2
1
0
TM2UD
—
—
—
ID
0
0
0
0
3
2
1
0
TM0UD
—
—
—
IE
0
0
0
0
3
2
1
0
TM1UD
—
—
—
ID
0
0
0
0
3
2
1
0
TM1
TM1
TM1
TM1
BR3
BR2
BR1
BR0
1
1
1
1
3
2
1
0
TM2
TM2
TM2
TM2
BR3
BR2
BR1
BR0
1
0
1
0
3
2
1
0
TM1
TM1
—
—
S1
S0
0
0
0
0
Panasonic Semiconductor Development Company
x'00FC71'
x'00FC70'
x'00FC73'
x'00FC72'
x'00FE11'
x'00FE12'
x'00FE21'
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