Panasonic MN10285K User Manual page 242

Closed-Caption Decoder
Closed-Caption Decoder Registers
MN102H75K/F75K/85K/F85K LSI User Manual
CRI1E: CRI Capture Stop Timing Control Register 1
(CRI1EW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
CRI1E[10:0]: Stop position for CRI capture 1
Valid range: x'000' to x'7FF'
CRI2S: CRI Capture Start Timing Control Register 2
(CRI2SW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
CRI2S[10:0]: Start position for CRI capture 2
Valid range: x'000' to x'7FF'
CRI2E: CRI Capture Stop Timing Control Register 2
(CRI2EW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
CRI2E[10:0]: Stop position for CRI capture 2
Set this field so that the last CRI rising edge is included. The valid range is
x'000' to x'7FF'.
DATAS: Data Capture Start Timing Control Register
(DATASW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
DATAS[10:0]: Start position for data capture
Set this field to the same start position as that for CRI detection (set in
CRI2S). The valid range is x'000' to x'7FF'.
241
Panasonic
11 10 9 8 7 6
CRI1E CRI1E CRI1E CRI1E CRI1E
—
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
11 10 9 8 7 6
CRI2S CRI2S CRI2S CRI2S CRI2S
—
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
11 10 9 8 7 6
CRI2E CRI2E CRI2E CRI2E CRI2E
—
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
11 10 9 8 7 6
DATA DATA DATA DATA DATA
— S S S S S
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
Panasonic Semiconductor Development Company
x'007E12'
x'007E32')
5 4 3 2 1
CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
x'007E14
x'007E34')
5 4 3 2 1
CRI2S CRI2S CRI2S CRI2S CRI2S CRI2S
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
x'007E16'
x'007E36')
5 4 3 2 1
CRI2E CRI2E CRI2E CRI2E CRI2E CRI2E
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
x'007E18'
x'007E38')
5 4 3 2 1
DATA DATA DATA DATA DATA DATA
S S S S S
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
0
0
1
0
0
1
0
0
1
0
S
0
1