H Counter Control Registers; Panasonic - Panasonic MN10285K User Manual

Panasonic Semiconductor Development Company

14.4 H Counter Control Registers

All registers in H Counter block cannot be written by byte (by word only). Read
by byte is possible.
HCCNT0: H Counter Control Register 0
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
SEDG0: Polarity select for count source signal (HI0)
0: Active low
1: Active high
SEDG0: Polarity select for reset signal
0: Active low
1: Active high
SELR20:00]: Reset signal select
000: 1024 µs
001: 2048 µs
010: 4096 µs
011: 8192 µs
100: VI0
101: VSYNC
All other settings default to 1024 µs.
HCCNT1: H Counter Control Register 1
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
SEDG1: Polarity select for count source signal (HI1)
0: Active low
1: Active high
SEDG1: Polarity select for reset signal
0: Active low
1: Active high
SELR[21:01]: Reset signal select
000: 1024 µs
001: 2048 µs
010: 4096 µs
011: 8192 µs
100: VI0
101: VSYNC
All other settings default to 1024 µs.
310

Panasonic

11 10 9 8 7 6
— — — — — —
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
— — — — — —
0 0 0 0 0 0
R R R R R R
MN102H75K/F75K/85K/F85K LSI User Manual
H Counter
H Counter Control Registers
x'007EB0'
5 4 3 2 1
SED RED SELR SELR SELR
—
G0 G0 20 10
0 0 0 0 0
R R/W R/W R/W R/W R/W
x'007EB2'
5 4 3 2 1
SED RED SELR SELR SELR
—
G1 G1 21 11
0 0 0 0 0
R R/W R/W R/W R/W R/W
0
00
0
0
01
0