Panasonic MN10285K User Manual page 240

Closed-Caption Decoder
Closed-Caption Decoder Registers
For designs using the closed-cap-
tion decoder, always tie the ACQ1
register to x'1312'.
MN102H75K/F75K/85K/F85K LSI User Manual
HNUM: HSYNC Count Register
(HNUMW
Bit: 15 14 13 12
VBI- VBI-
— — — IRQ IRQ
4
Reset: 0 0 0 1
R/W: R R R R/W R/W
This register allows you to time the interrupt occurring after the line 21
data capture to a line other than line 21.
VBIIRQ[4:0]: VBI interrupt timing control
In this field, set the H line number, from 0 to 25, for the VBI interrupt. You
must set this field to x'13' or higher.
SBFLAG: Start bit detection flag
0: No start bit detected
1: Start bit detected
HNUM[4:0]: HSYNC count during the VBI interval
This field indicates the H line number, from 0 to 25.
ACQ1: ACQ Capture Timing Control Register 1
(ACQ1W
Bit: 15 14 13 12
ACQ1 ACQ1
— — —
E4 E3
Reset: 0 0 0 1
R/W: R R R R/W R/W
ACQ1E[4:0]: Stop position for ACQ capture 1
Valid range: x'00' to x'25'
ACQ1S[4:0]: Start position for ACQ capture 1
Valid range: x'00' to x'25'
CAPDATA: Caption Data Capture Register
(CAPDATAW
Bit: 15 14 13 12
CAP CAP CAP CAP CAP
DA15 DA14 DA13 DA12 DA11
Reset: 0 0 0 0
R/W: R R R R
CAPDA[15:0]: Caption data
This register stores the 16-bit captured caption data.
239
Panasonic
11 10 9 8 7 6
VBI- VBI- VBI-
SB
IRQ IRQ IRQ —
FLAG
3 2 1 0
1 1 1 1 0 0
R/W R/W R/W R R
11 10 9 8 7 6
ACQ1 ACQ1 ACQ1
— —
E2 E1 E0
1 1 1 1 0 0
R/W R/W R/W R R
11 10 9 8 7 6
CAP CAP CAP CAP CAP
DA10 DA9 DA8 DA7 DA6
0 0 0 0 0 0
R R R R R R
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x'007E06'
x'007E26')
5 4 3 2 1 0
HNU HNU HNU HNU HNU
—
M4 M3 M2 M1 M0
0 0 0 0 0 0
R R R R R R
x'007E08'
x'007E28')
5 4 3 2 1 0
ACQ1 ACQ1 ACQ1 ACQ1 ACQ1
—
S4 S3 S2 S1 S0
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
x'007E0A'
x'007E2A')
5 4 3 2 1 0
CAP CAP CAP CAP CAP CAP
DA5 DA4 DA3 DA2 DA1 DA0
0 0 0 0 0 0
R R R R R R