External Reset Control Timing (Timer 5); Panasonic - Panasonic MN10285K User Manual

Panasonic Semiconductor Development Company
TM5CA (example)
Bit: 15 14 13 12
TM5 TM5 TM5 TM5 TM5
CA15 CA14 CA13 CA12 CA11
Setting: 0 0 0 1
3. Set the TM5NLD bit of the TM5MD register to 1 and the TM5EN bit to 0.
This enables TM5BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle.
4. Set TM5NLD and TM5EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
From this point on, whenever the TM5IC signal is high, timer 5 will be reset
asynchronously. This is an easy way to synchronize the microcontroller operation
with an external event. You can use it to adjust motor speed or to initialize the
timers through the hardware.
Timer 5 does not operate in STOP mode, when B
clock, it must be synchronized to B
Figure 4-53 shows an example timing chart.
0000 0001 0002
TM5BC
B /4
OSC
TM5IC
Figure 4-53 External Reset Control Timing (Timer 5)
124

Panasonic

11 10 9 8 7 6
TM5 TM5 TM5 TM5 TM5
CA10 CA9 CA8 CA7 CA6
1 1 1 1 1 1
.
OSC
0003 0004 0000
MN102H75K/F75K/85K/F85K LSI User Manual
Timers
16-Bit Timer Setup Examples
x'00FE94'
5 4 3 2 1
TM5 TM5 TM5 TM5 TM5
CA5 CA4 CA3 CA2 CA1
1 1 1 1 1
is off. If you use an external
OSC
0001 0002
0
TM5
CA0
1
0003