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2
I
C Bus Controller
2
I
C Bus Interface Registers
MN102H75K/F75K/85K/F85K LSI User Manual
2
I2CDREC: I
C Reception Data Register
Bit:
15
14
13
12
MODE
MODE
—
STS
LRB
1
0
Reset:
0
0
0
0
R/W:
R
R
R
R
The I2CDREC register contains the status bits for monitoring the device
and the reception data. I2CDREC is a read-only register.
2
MODE[1:0]: I
C device mode
This field indicates which I
indicates slave or master, and MODE0 indicates receiver or transmitter. If
the microcontroller loses an arbitration or if a stop condition occurs, the
hardware clears MODE[1:0] to b'00'.
00: Slave receiver
01: Slave transmitter
STS: Stop condition at slave receiver
Set to 1 when a stop condition is detected while the microcontroller is in
slave receiver mode.
LRB: Last received bit.
Stores the last serial data bit received. LRB normally indicates the ACK
cycle data.
AAS: Addressed as slave
Set to 1 when the slave address on the bus matches the contents of the
address register or matches the general address (x'00'). AAS resets after a
read from the I2CDREC register.
LAB: Lost arbitration bit
Set to 1 when the microcontroller loses a bus arbitration. LAB resets when
I2CDTRM indicates a start condition (STA = 1).
BB: Bus busy bit
A start condition on the bus sets this flag to 0, and a stop condition resets it
to 1. The microcontroller considers the bus to be busy as long as BB = 0.
D[7:0]: Received data
The serial data received from the I
first.
2
I2CMYAD: I
C Self Address Register
Bit:
15
14
13
12
—
—
—
—
Reset:
0
0
0
0
R/W:
R
R
R
R
A[6:0]: Microcontroller address
This register is formed from a 7-bit field address latch. It holds the micro-
controller's own address, used for a compare when the microcontroller is
addressed as a slave. When a match occurs, AAS is set to 1.
305
Panasonic
11
10
9
8
7
6
AAS
LAB
BB
D7
D6
0
0
0
1
0
0
R
R
R
R
R
R
2
C mode the microcontroller is in. MODE1
10: Master receiver
11: Master transmitter
2
C bus is shifted into this field MSB
11
10
9
8
7
6
—
—
—
—
—
A6
0
0
0
0
0
0
R
R
R
R
R
R/W
Panasonic Semiconductor Development Company
x'007E42'
5
4
3
2
1
0
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
R
R
R
R
R
R
x'007E44'
5
4
3
2
1
0
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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