Panasonic MN10285K User Manual page 59

Panasonic Semiconductor Development Company
TM5UDICH: Timer 5 Underflow Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
TM5UDICH enables timer 5 underflow interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
The priority level for timer 5 underflow interrupts is written to the
TM5CBLV[2:0] field of the TM5CBICH register.
TM5UDIE: Timer 5 underflow interrupt enable flag
0: Disable
1: Enable
VBIWICL: VBI (2) Interrupt Control Register (Low)
Bit: 7 6 5 4
VBIW
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
VBIWICL detects and requests VBI (2) interrupts. It is an 8-bit access reg-
ister. Use the MOVB instruction to access it.
VBIWIR: VBI (2) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIWID: VBI (2) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIWICH: VBI (2) Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
VBIWICH register enables VBI (2) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
The priority level for VBI (2) interrupts is written to the TM5CBLV[2:0]
field of the TM5CBICH register.
VBIWIE: VBI (2) interrupt enable flag
0: Disable
1: Enable
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Panasonic
Interrupt Control Registers
3 2 1 0
TM5UD
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
VBIW
— — —
ID
0 0 0 0
R R R R
3 2 1 0
VBIW
— — —
IE
0 0 0 0
R R R R/W
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
x'00FC6D'
x'00FC6E'
x'00FC6F'