Panasonic MN10285K User Manual page 67

Panasonic Semiconductor Development Company
SCR0ICH: Serial 0 Reception End Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
SCR0ICH enables serial 0 reception end interrupts. It is an 8-bit access
register. Use the MOVB instruction to access it.
The priority level for serial 0 reception end interrupts is written to the
ANLV[2:0] field of the ANICH register.
SCR0IE: Serial 0 reception end interrupt enable flag
0: Disable
1: Enable
VBIVICL: VBIVSYNC (1) Interrupt Control Register (Low)
Bit: 7 6 5 4
— — — VBIVIR
Reset: 0 0 0 0
R/W: R R R R/W
VBIVICL detects and requests VBIVSYNC (1) interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
VBIVIR: VBIVSYNC (1) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIVID: VBIVSYNC (1) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIVICH: VBIVSYNC (1) Interrupt Control Register (High)
Bit: 7 6 5 4
VBIV VBIV VBIV
—
LV2 LV1 LV0
Reset: 0 0 0 0
R/W: R R/W R/W R/W
VBIVICH sets the priority level for and enables VBIVSYNC (1) inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
VBIVLV[2:0]: VBIVSYNC (1) interrupt priority level
Sets the priority from 0 to 6.
VBIVIE: VBIVSYNC (1) interrupt enable flag
0: Disable
1: Enable
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Panasonic
Interrupt Control Registers
3 2 1 0
SCR0
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
— — — VBIVID
0 0 0 0
R R R R
3 2 1 0
VBIV
— — —
IE
0 0 0 0
R R R R/W
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
x'00FC85'
x'00FC88'
x'00FC89'