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Timers
16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
With PWM output, the duty cycle can change dynamically, which can cause the
PWM waveform to skip a pulse (see the single buffering section of figure 4-34
below). To prevent these misses, timers 4 and 5 provide a double-buffer mode. In
this mode, no matter what the timing of a TMnCB change, the duty change does
not occur until the beginning of the next cycle, and no signals are lost. Per-
formance is assured even when the output switches from all 1s to all 0s (see the
double buffering section of figure 4-34 below).
For this reason, you must always use double-buffer mode for PWM waveform
output. Use single-buffer mode only in applications that are unaffected by this
issues.
TM4EN
Write to TM4CB
TM4CB
0
0
1
2
TM4BC
B
/4
OSC
CLRBC4
(1) Double buffering
TM4CB
TM4CBX
B4
A4
TM4OA
TM4OB
Interrupts
(2) Single buffering
TM4CB
B4
A4
TM4OA
TM4OB
Interrupts
Figure 4-34 Two-Phase PWM Output Timing with Dynamic Duty Changes
105
Panasonic
3
3
4
0
1
2
3
4
0
3
3
B
A
B
A
No PWM or interrupt errors
3
A
A
B
Lost interrupt, causing a PWM output error
(Timer 4)
Panasonic Semiconductor Development Company
1
1
2
3
4
0
1
2
3
1
1
B
A
B
1
B
A
B
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