Toshiba DP120F Service Manual page 364

• DMAC GA Signal Table (2/7)
No. Signal Name
18 MWRHX
19 MWRLX
20 MWRX
21-27, 29-32 SDA0-9
33 SRAS0
34 SRAS1
35, 37 SCAS0L, H
38, 39 SCAS1L, H
40 SDOEX
41 SDWEX
42, 79, 102, 3.3V
113, 121,
131, 141,
181, 210
43 BGACKX
44 BRX
I: Input O: Output
March 2000 © TOSHIBA TEC
Type
O SRAM write signal (active-low)
Write signal for SRAM (IC31).
O SRAM write signal (active-low)
Write signal for SRAM (IC30).
O Flash ROM write signal (active-low)
Write signal for Flash ROM (IC13, IC20).
O System address bus
Address bus for SYS-DRAM (IC34, IC41), SYS-
DRAM (IC46), DRAM (IC1, IC2) on the Memory PBA.
O System RAS0 signal
RAS signal for SYS-DRAM (IC34, IC41) and SYS-
DRAM (IC46).
O System RAS 1 signal
RAS signal for DRAM (IC1, IC2) on the Memory PBA.
O System CAS0L and CAS0H signals
CAS signals for SYS-DRAM (IC34), SYS-DRAM
(IC46), and DRAM (IC1) on the Memory PBA.
O System CAS1L and CAS1H signals
CAS signals for SYS-DRAM (IC41) and DRAM (IC2)
on the Memory PBA.
O System read signal
Read signal for SYS-DRAM (IC34, IC41), SYS-
DRAM (IC46), and DRAM (IC1, IC2) on the Memory
PBA.
O System write signal
Write signal for SYS-DRAM (IC34, IC41), SYS-
DRAM (IC46), and DRAM (IC1, IC2) on the Memory
PBA.
- +3.3V
O Bus ground acknowledge signal (active-low)
Indicates the fact of becoming the bus master to the
CPU (IC66).
O Bus request signal (active-low)
Requests the CPU for bus control.
I/O: Bidirectional
Functions
7-55 DP120F/DP125F Circuit Description