Toshiba DP120F Service Manual page 362

Pin Function Table
• CPU Signal Table
No. Signal Name
1 RWX
2 DTACKX
3 BGX
4 BRX
5,41 +5V
6 CPUCK
7, 23, 56 SG
8 MODE
9 HALTX
10 RESETX
11 AVECX
12 BERR
13-15 IPL2-0X
16-18 FC2-0
19 A0
20-22, 24-40, A1-23
42-44
45-55, 57-61 D0-15
62 ASX
63 UDSX
64 LDSX
I: Input O: Output
March 2000 © TOSHIBA TEC
Type
O Read/write signal (H: Read, L: Write)
Requests each IC to read or write data.
I Data transfer acknowledge (active-low)
The DMAC GA (IC16) indicates the end of data trans-
fer.
O Bus ground (active-low)
Indicates the release of the bus to the DMAC GA.
I Bus request (active-low)
The DMAC GA makes a request for bus control.
- +5V
I CPU operation clock (16MHz)
- Signal ground
- +5V
O Halt signal (active-low)
Indicates that the CPU (IC66) is stopped.
I Reset signal (active-low)
Resets the system.
- +5V
- +5V
I Interrupt request 0-2 signals (active-low)
The DMAC GA makes requests for interrupt process-
ing.
O CPU operating status 0-2 signals
Indicate the operating status of the CPU to the DMAC
GA.
- Unused
O Address bus
I/O Data bus
O Address strobe signal (active-low)
Causes the address bus data to be latched.
O Upper data strobe signal (active-low)
Causes the upper data bus data to be latched.
O Lower data strobe signal (active-low)
Causes the lower data bus data to be latched.
I/O: Bidirectional
Functions
7-53 DP120F/DP125F Circuit Description