Oracle Exadata X10M Service Manual page 260

AMD CBS Option
DDR Power Options
Sub Urgent Refresh Lower Bound
Urgent Refresh Limit
DRAM Refresh Rate
Self-Refresh Exit Staggering
Double Data Rate Self-Testing Memory
Built-in Self Test (DDR MBIST) Options
DDR Healing BIST Options
DDR Healing BIST Execution Mode
PMU Mem BIST Algorithm
DDR Healing BIST Repair Type
Double Data Rate Row Address Strobe
(DDR RAS)
Disable Memory Error Injection
DDR Security
TSME
SME-MK
Non-blocking Input Output (NBIO)
Options
IOMMU
ACS Enable
Description
With Force APCB Update enabled, allows you to specify the stored
refresh limit required to enter sub-urgent refresh mode. The
minimum limit is 1 and the maximum limit is 6. Default is 1.
With Force APCB Update enabled, allows you to specify the stored
refresh limit required to enter urgent refresh mode. The minimum
limit is 1 and the maximum limit is 6. Default is 4.
With Force APCB Update enabled, allows you to specify the DRAM
refresh rate to 3.9 usec (default) or 1.95 usec.
With Force APCB Update enabled, allows you to specify the amount
to stagger the self-refresh exit. Tcksrx += (Trfc/n * (UMC_Number %
3)) To disable staggering, select n=1. Default is n=9.
With Force APCB Update enabled, allows you to enable or disable
(default) running a full memory content test and is separate and
distinct from the MBIST test of Interface and Data Eye. The PMU
Mem BIST option uses PMU firmware to test the memory on all
channels simultaneously. Failing memory is repaired using soft or
hard PPR, depending on the PPR configuration. The Self-Healing
Mem BIST option runs the JEDEC DRAM self healing test, if the
device and DIMM support the self-healing. The DRAM does a hard
repair for any failing memory. The Power Management Unit (PMU)
and Self-Healing Mem BIST option runs the PMU Mem BIST and
then the Self-Healing Mem BIST tests sequentially.
With Force APCB Update enabled, enables a memory content test.
With Force APCB Update enabled, allows you to select PMU Mem
BIST algorithms.
With Force APCB Update enabled, for DRAM errors found in the
BIOS memory BIST, select the repair type: Soft, Hard, or Test only.
Do not attempt to repair.
With Force APCB Update enabled, allows you to specify the Unified
Management Console (UMC) error injection configuration where
writes are disabled. Default is Auto.
With Force APCB Update enabled, allows you to enable or disable
transparent SME. Default is Auto.
With Force APCB Update enabled, allows you to enable or disable
(default) SME-MK encryption mode. Enabling both SMEE and SME-
MK is not supported.
With Force APCB Update enabled, allows you to enable or disable
I/O Memory Management Unit (IOMMU). Default is Auto.
With Force APCB Update enabled, allows you to enable or disable
Access Control Services (ACS). You must enable Advanced Error
Reporting (AER) for ACS to work. Default is Auto.
Appendix F
Advanced Menu
F-5