NEC 78K0/KD1 Series User Manual page 106

Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 00H
Symbol 7
PCC MCC
MCC
0
1
FRC
0
1
CLS
0
1
Note 4
CSS
0
1
Notes 1. Bit 5 is read-only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator
operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC
control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP
instruction should not be used.
3. The feedback resistor is required to adjust the bias point of the oscillation waveform to close to the
middle of the power supply voltage. Setting FRC to 1 can further reduce the current consumption in
the STOP mode, but only when the subsystem clock is not used.
4. Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Caution Be sure to set bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
2. f : Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock
X
oscillation frequency)
3. f : Ring-OSC clock oscillation frequency
R
4. f : X1 input clock oscillation frequency
XP
5. f : Subsystem clock oscillation frequency
XT
106
CHAPTER 5 CLOCK GENERATOR
Note 1
R/W
6 5
FRC CLS
Control of X1 oscillator operation
Oscillation possible
Oscillation stopped
Subsystem clock feedback resistor selection
On-chip feedback resistor used
On-chip feedback resistor not used
X1 input clock or Ring-OSC clock
Subsystem clock
PCC2 PCC1 PCC0
0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
Other than above
Preliminary User's Manual U16315EJ1V0UD
4 3 2
CSS 0 PCC2
CPU clock status
CPU Clock (f
0 f f
X R
1 f /2 f /2
X R
2
0 f /2 f /2
X R
3
1 f /2 f /2
X R
4
0 f /2 f /2
X R
0 f /2
XT
1
0
1
0
Setting prohibited
1 0
PCC1 PCC0
Note 2
Note 3
) Selection
CPU
MCM0 = 0 MCM0 = 1
f
XP
f /2
XP
2 2
f /2
XP
3 3
f /2
XP
4 4
f /2
XP