(3) Priority specification flag registers (PR0L, PR0H, PR1L)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 16-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L)
Address: FFE8H
After reset: FFH
Symbol
7
PR0L
SREPR6
Address: FFE9H
After reset: FFH
Symbol
7
PR0H
TMPR010
Address: FFEAH
After reset: FFH
Symbol
7
Note
PR1L
1
XXPRX
0
1
Note Be sure to set bit 7 of PR1L to 1.
CHAPTER 16 INTERRUPT FUNCTIONS
R/W
6
5
PPR5
PPR4
PPR3
R/W
6
5
TMPR000
TMPR50
TMPRH0
R/W
6
5
PPR6
WTPR
KRPR
High priority level
Low priority level
Preliminary User's Manual U16315EJ1V0UD
4
3
2
PPR2
PPR1
4
3
2
TMPRH1
DUALPRO
4
3
2
TMPR51
WTIPR
Priority level selection
1
0
PPR0
LVIPR
1
0
STPR6
SRPR6
1
0
SRPR0
ADPR
331