NEC 78K0/KD1 Series User Manual page 187

(2) Timing chart
The timing in interval timer mode is shown below.
Count clock
Count start
00H
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
<1>
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.
<3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn
operation. If these are inactive from the first, the level is retained.
Remark n = 0, 1
N = 00H to FFH
CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-7. Timing of Interval Timer Operation (1/2)
(a) Basic operation
01H N
N
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
Preliminary User's Manual U16315EJ1V0UD
00H 01H
Clear
Interval time
match interrupt occurrence,
8-bit timer counter Hn clear
N 00H 01H 00H
Clear
<3>
<2>
Level inversion,
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