NEC 78K0/KD1 Series User Manual page 166

Figure 7-4. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH After reset: 00H
Symbol 7
TCL51 0
TCL512
0
0
0
0
1
1
1
1
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to set bits 3 to 7 to 0.
Remarks 1. f : X1 input clock oscillation frequency
X
2. Figures in parentheses apply to operation at f
166
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R/W
6 5
0 0
TCL511 TCL510
0 0 TI51 falling edge
0 1 TI51 rising edge
1 0 f (10 MHz)
X
1 1 f /2 (5 MHz)
X
4
0 0 f /2
X
6
0 1 f /2
X
8
1 0 f /2
X
12
1 1 f /2
X
Preliminary User's Manual U16315EJ1V0UD
4 3 2
0 0 TCL512
Count clock selection
(625 kHz)
(156.25 kHz)
(39.06 kHz)
(2.44 kHz)
= 10 MHz.
X
1 0
TCL511 TCL510