Interrupt Servicing Operations; Maskable Interrupt Request Acknowledgement - NEC 78K0/KD1 Series User Manual

16.4 Interrupt Servicing Operations

16.4.1 Maskable interrupt request acknowledgement

A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask
(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if
interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is
not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table
16-4 below.
For the interrupt request acknowledgement timing, see Figures 16-8 and 16-9.
Table 16-4. Time from Generation of Maskable Interrupt Request Until Servicing
When ××PR = 0
When ××PR = 1
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
CPU
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 16-7 shows the interrupt request acknowledgement algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the
PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
334
CHAPTER 16 INTERRUPT FUNCTIONS
Minimum Time
7 clocks
8 clocks
(f : CPU clock)
CPU
Preliminary User's Manual U16315EJ1V0UD
Note
Maximum Time
32 clocks
33 clocks