Operation Of Clock Monitor - NEC 78K0/KD1 Series User Manual

20.4 Operation of Clock Monitor

This section explains the functions of the clock monitor. The start and stop conditions are as follows.
<Start condition>
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1).
<Stop condition>
• In STOP mode and during the oscillation stabilization time
• During the oscillation stabilization time after reset is released
• When the X1 input clock is stopped by software (when MSTOP = 1 or MCC = 1)
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
Table 20-2. Operation Status of Clock Monitor (When CLME = 1)
CPU Operation Clock Operation Mode
X1 input clock STOP mode
RESET input
HALT mode
Ring-OSC clock STOP mode
RESET input
HALT mode
Note The Ring-OSC clock is stopped only when the "Ring-OSC can be stopped by software" is selected by a
mask option. If "Ring-OSC cannot be stopped" is selected, the Ring-OSC clock cannot be stopped.
The clock monitor timing is as shown in Figure 20-3.
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CHAPTER 20 CLOCK MONITOR
X1 Input Clock Status
Stopped Oscillating
Stopped
Oscillating
Stopped
Oscillating Oscillating
Stopped
Stopped Oscillating
Oscillating
Stopped
Preliminary User's Manual U16315EJ1V0UD
Ring-OSC Clock Status Clock Monitor Status
Stopped
Note
Note
Operating
Note
Stopped
Stopped
Operating
Stopped