NEC 78K0/KD1 Series User Manual page 111

(6) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released.
The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU
clock. After STOP mode is released with Ring-OSC selected as CPU clock, the oscillation stabilization time must
be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 5-8. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H
Symbol 7
OSTS 0
OSTS2
0
0
0
1
1
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is
Remarks 1. Values in parentheses are for operation with f
CHAPTER 5 CLOCK GENERATOR
R/W
6 5
0 0
OSTS1 OSTS0
0 1
1 0
1 1
0 0
0 1
Other than above
being used as the CPU clock, set the oscillation stabilization time as follows.
• • • • Desired OSTC oscillation stabilization time ≤ ≤ ≤ ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
2. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts ("a" below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
V
SS
2. f : X1 input clock oscillation frequency
XP
Preliminary User's Manual U16315EJ1V0UD
4 3
0 0 OSTS2
Oscillation stabilization time selection
(204.8 µ s)
11
2 /f
XP
(819.2 µ s)
13
2 /f
XP
14
2 /f (1.64 ms)
XP
15
2 /f (3.27 ms)
XP
16
2 /f (6.55 ms)
XP
Setting prohibited
a
= 10 MHz.
XP
2 1 0
OSTS1 OSTS0
111