NEC 78K0/KD1 Series User Manual page 134

Figure 6-2. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address FFBAH After reset: 00H
Symbol 7 6 5
TMC00 0 0 0
TMC003 TMC002 TMC001
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
OVF00
0 Overflow not detected
1 Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
3. If any of the following modes: the mode in which clear & start occurs on match between
TM00 and CR000, the mode in which clear & start occurs at the TI00 valid edge, or free-
running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes
from FFFFH to 0000H, the OVF00 flag is set to 1.
Remarks 1. TO00: 16-bit timer/event counter 00 output pin
2. TI000: 16-bit timer/event counter 00 input pin
3. TM00: 16-bit timer counter 00
4. CR000: 16-bit timer capture/compare register 000
5. CR010: 16-bit timer capture/compare register 010
134
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
R/W
4 3 2 1
0 TMC003 TMC002 TMC001 OVF00
Operating mode and clear
mode selection
Operation stop
(TM00 cleared to 0)
Free-running mode
Clear & start occurs on TI000
valid edge
Clear & start occurs on match
between TM00 and CR000
16-bit timer counter 00 (TM00) overflow detection
Preliminary User's Manual U16315EJ1V0UD
0
TO00 output timing selection
No change
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 valid edge
−
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 valid edge
Interrupt request generation
Not generated
Generated on match between
TM00 and CR000, or match
between TM00 and CR010