NEC 78K0/KD1 Series User Manual page 107

The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KD1 Series. Therefore, the
relationship between the CPU clock (f
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (f )
CPU
0.2 µ s
f
X
0.4 µ s
f /2
X
0.8 µ s
2
f /2
X
1.6 µ s
3
f /2
X
3.2 µ s
4
f /2
X
f /2
XT
Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see
Figure 5-5).
(2) Ring-OSC mode register (RCM)
This register sets the operation mode of Ring-OSC.
This register is valid when "Can be stopped by software" is set for Ring-OSC by a mask option, and the X1 input
clock or subsystem clock is selected as the CPU clock. If "Cannot be stopped" is selected for Ring-OSC by a
mask option, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FFA0H After reset: 00H
Symbol 7
RCM 0
RSTOP
0
1
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
CHAPTER 5 CLOCK GENERATOR
) and minimum instruction execution time is as shown in the Table 5-2.
CPU
Minimum Instruction Execution Time: 2/f
Note
X1 Input Clock
(at 10 MHz Operation)
−
Figure 5-4. Format of Ring-OSC Mode Register (RCM)
R/W
6 5
0 0
Ring-OSC oscillating
Ring-OSC stopped
setting RSTOP.
Preliminary User's Manual U16315EJ1V0UD
Note
Ring-OSC Clock
(at 240 kHz (TYP.) Operation)
8.3 µ s (TYP.)
16.6 µ s (TYP.)
33.2 µ s (TYP.)
66.4 µ s (TYP.)
132.8 µ s (TYP.)
−
4 3
0 0
Ring-OSC oscillating/stopped
CPU
Subsystem Clock
(at 32.768 kHz Operation)
−
−
−
−
−
122.1 µ s
2 1 0
0 0 RSTOP
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