Registers Controlling Standby Function - NEC 78K0/KD1 Series User Manual

18.1.2 Registers controlling standby function

The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), STOP instruction, MSTOP =
1, and MCC = 1 clear OSTC to 00H.
Figure 18-2. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H
Symbol 7
OSTC 0
MOST11
1
1
1
1
1
Caution After the above time has elapsed, the bits are set to 1 in order from MOST11 and
Remarks 1. Values in parentheses are for operation with f
CHAPTER 18 STANDBY FUNCTION
R
6 5
0 0
MOST13 MOST14
0 0
1 0
1 1
1 1
1 1
remain 1.
2. f : X1 input clock oscillation frequency
X
Preliminary User's Manual U16315EJ1V0UD
4 3
MOST11 MOST13 MOST14
MOST15 MOST16 Oscillation stabilization time status
11
0 0 2 /f
X
13
0 0 2 /f
X
14
0 0 2 /f
X
15
1 0 2 /f
X
16
1 1 2 /f
X
= 10 MHz.
X
2 1 0
MOST15 MOST16
min. (204.8 µ s min.)
min. (819.2 µ s min.)
min. (1.64 ms min.)
min. (3.27 ms min.)
min. (6.55 ms min.)
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