Configuration Of Watchdog Timer - NEC 78K0/KD1 Series User Manual

10.2 Configuration of Watchdog Timer

The watchdog timer consists of following hardware.
Control registers
Clock
2
f /2
R
input
4
f /2
XP
controller
2
Watchdog timer enable
register (WDTE)
CHAPTER 10 WATCHDOG TIMER
Table 10-3. Configuration of Watchdog Timer
Item
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 10-1. Block Diagram of Watchdog Timer
13
f /2 to
XP
20
f /2
XP
16-bit
counter
or
11
f /2 to
R
18
f /2
R
Clear
0 1 1
WDCS4
Watchdog timer mode
register (WDTM)
Internal bus
Preliminary User's Manual U16315EJ1V0UD
Configuration
Output
Selector
controller
3 3
WDCS3 WDCS2 WDCS1 WDCS0
WDTRES
(internal reset signal)
Mask option
(to set "Ring-OSC
cannot be stopped" or
"Ring-OSC can be
stopped by software")
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