NEC 78K0/KD1 Series User Manual page 221

Figure 11-2. Format of Clock Output Selection Register (CKS)
Address: FF40H After reset: 00H
Symbol 7
CKS 0
CLOE
0 Clock division circuit operation stopped. PCL fixed to low level.
1 Clock division circuit operation enabled. PCL output enabled.
CCS3
0
0
0
0
0
0
0
0
1
Remarks 1. f : X1 input clock oscillation frequency
X
2. f : Subsystem clock oscillation frequency
XT
3. Figures in parentheses are for operation with f
CHAPTER 11 CLOCK OUTPUT CONTROLLER
R/W
6 5 4
0 0 CLOE
PCL output enable/disable specification
CCS2 CCS1 CCS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
Other than above
Preliminary User's Manual U16315EJ1V0UD
3 2
CCS3 CCS2
PCL output clock selection
f (10 MHz)
X
f /2 (5 MHz)
X
2
f /2 (2.5 MHz)
X
3
f /2 (1.25 MHz)
X
4
f /2 (625 kHz)
X
5
f /2 (312.5 kHz)
X
6
f /2 (156.25 kHz)
X
7
f /2 (78.125 kHz)
X
f (32.768 kHz)
XT
Setting prohibited
= 10 MHz or f = 32.768 kHz.
X XT
1 0
CCS1 CCS0
221