NEC 78K0/KD1 Series User Manual page 365

CHAPTER 20 CLOCK MONITOR
Figure 20-3. Timing of Clock Monitor (3/3)
(5) Clock monitor status after RESET input
(CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
Normal
Clock supply
operation
CPU operation Reset stopped Normal operation (Ring-OSC clock)
X1 input clock
Oscillation stabilization time
Ring-OSC clock
17 clocks
RESET
Set to 1 by software
CLME
Clock monitor status
Monitoring Monitoring stopped Monitoring
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. When CLME is set to 1 by software at the end of the oscillation stabilization time of the X1 input clock,
monitoring is started.
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Preliminary User's Manual U16315EJ1V0UD