NEC 78K0/KD1 Series User Manual page 108

(3) Main clock mode register (MCM)
This register sets the CPU clock (X1 input clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FFA1H After reset: 00H
Symbol 7
MCM 0
MCS
0
1
MCM0
0
1
Note Bit 1 is read-only.
Cautions 1. When Ring-OSC clock is selected as the clock to be supplied to the CPU, the
108
CHAPTER 5 CLOCK GENERATOR
Figure 5-5. Format of Main Clock Mode Register (MCM)
Note
R/W
6 5
0 0
Operates with Ring-OSC clock
Operates with X1 input clock
Ring-OSC clock
X1 input clock
divided clock of the Ring-OSC oscillator output (f
hardware (f = 240 kHz (TYP.)).
X
Operation of the peripheral hardware with Ring-OSC clock cannot be
guaranteed. Therefore, when Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the clock supplied to the CPU from the X1 input clock
to the Ring-OSC clock. Note, however, that the following peripheral hardware
can be used when the CPU operates on the Ring-OSC clock.
• • • • Watchdog timer
• • • • Clock monitor
• • • • 8-bit timer H1 when f
• • • • Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM00 is selected (TI000 valid edge))
2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1
input clock operation (bit 4 (CSS) of the processor clock control register (PCC)
is changed from 1 to 0).
Preliminary User's Manual U16315EJ1V0UD
4 3
0 0
CPU clock status
Selection of clock supplied to CPU
7
/2 is selected as count clock
R
2 1 0
0 MCS MCM0
) is supplied to the peripheral
X