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X1
CPU clock
Normal operation
RESET
Internal
reset signal
Port pin
Figure 19-3. Timing of Reset Due to Watchdog Timer Overflow
X1
Normal operation
CPU clock
Watchdog
timer
overflow
Internal
reset signal
Port pin
Caution A watchdog timer internal reset resets the watchdog timer.
X1
CPU clock
Normal operation
RESET
Internal
reset signal
Port pin
Note The port pins become high impedance, except for P130, which is set to low-level output.
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 21 POWER-
ON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR.
356
CHAPTER 19 RESET FUNCTION
Figure 19-2. Timing of Reset by RESET Input
Reset period
(Oscillation stop)
Delay
Reset period
(Oscillation stop)
Figure 19-4. Timing of Reset in STOP Mode by RESET Input
STOP instruction execution
Stop status
(Oscillation stop)
Delay
Preliminary User's Manual U16315EJ1V0UD
Operation
Normal operation
stop
(Reset processing, Ring-OSC clock)
(17/f
)
R
Delay
Note
Hi-Z
Operation
Normal operation
stop
(Reset processing, Ring-OSC clock)
(17/f
)
R
Note
Hi-Z
Operation
Reset period
stop
(Oscillation stop)
(17/f
)
R
Delay
Note
Hi-Z
Normal operation
(Reset processing, Ring-OSC clock)
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