NEC 78K0/KD1 Series User Manual page 18

Figure No.
10-1 Block Diagram of Watchdog Timer ............................................................................................................211
10-2 Format of Watchdog Timer Mode Register (WDTM) .................................................................................212
10-3 Format of Watchdog Timer Enable Register (WDTE)................................................................................213
10-4 Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) .................................216
10-5 Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock) ...........216
10-6 Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock) ...........217
10-7 Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) ..............................218
10-8 Operation in HALT Mode...........................................................................................................................218
11-1 Block Diagram of Clock Output Controller .................................................................................................219
11-2 Format of Clock Output Selection Register (CKS).....................................................................................221
11-3 Format of Port Mode Register 14 (PM14)..................................................................................................222
11-4 Remote Control Output Application Example ............................................................................................223
12-1 Block Diagram of A/D Converter ...............................................................................................................224
12-2 Block Diagram of Power-Fail Detection Function ......................................................................................225
12-3 Format of A/D Conversion Register (ADCR) .............................................................................................226
12-4 Format of A/D Converter Mode Register (ADM) ........................................................................................228
12-5 Timing Chart When Boost Reference Voltage Generator Is Used.............................................................229
12-6 Format of Analog Input Channel Specification Register (ADS) .................................................................230
12-7 Format of Power-Fail Comparison Mode Register (PFM)..........................................................................231
12-8 Format of Power-Fail Comparison Threshold Register (PFT) ...................................................................231
12-9 Basic Operation of A/D Converter .............................................................................................................233
12-10 Relationship Between Analog Input Voltage and A/D Conversion Result..................................................234
12-11 A/D Conversion Operation.........................................................................................................................235
12-12 Power-Fail Detection (When PFEN = 1 and PFCM = 0)............................................................................236
12-13 Overall Error ..............................................................................................................................................238
12-14 Quantization Error .....................................................................................................................................238
12-15 Zero-Scale Error ........................................................................................................................................239
12-16 Full-Scale Error .........................................................................................................................................239
12-17 Integral Linearity Error ...............................................................................................................................239
12-18 Differential Linearity Error..........................................................................................................................239
12-19 Circuit Configuration of Series Resistor String ..........................................................................................240
12-20 Storing Conversion Result in ADCR and Timing of Data Read from ADCR ..............................................241
12-21 Analog Input Pin Connection .....................................................................................................................242
12-22 Timing of A/D Conversion End Interrupt Request Generation ...................................................................243
12-23 Timing of A/D Converter Sampling and A/D Conversion Start Delay ........................................................244
13-1 Block Diagram of Serial Interface UART0 .................................................................................................247
13-2 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) ........................................249
13-3 Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) ..............................251
13-4 Format of Baud Rate Generator Control Register 0 (BRGC0)...................................................................252
13-5 Format of Normal UART Transmit/Receive Data ......................................................................................257
13-6 Example of Normal UART Transmit/Receive Data Format........................................................................257
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LIST OF FIGURES (4/7)
Title
Preliminary User's Manual U16315EJ1V0UD
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