Register For Confirming Reset Source - NEC 78K0/KD1 Series User Manual

19.1 Register for Confirming Reset Source

Many internal reset generation sources exist in the 78K0/KD1 Series. The reset control flag register (RESF) is
used to store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Address: FFACH After reset: 00H
Symbol 7
RESF 0
WDTRF
0
1
CLMRF
0
1
LVIRF
0
1
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 19-2.
Reset Source
Flag
WDTRF
CLMRF
LVIRF
CHAPTER 19 RESET FUNCTION
Figure 19-5. Format of Reset Control Flag Register (RESF)
Note
R
6 5
0 0
Internal reset request by watchdog timer (WDT)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request by clock monitor (CLM)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request by low-voltage detector (LVI)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Table 19-2. RESF Status When Reset Request Is Generated
RESET input Reset by POC
Cleared (0) Cleared (0)
Preliminary User's Manual U16315EJ1V0UD
4 3
WDTRF 0
Reset by WDT Reset by CLM
Set (1) Held
Held Set (1)
Held Held
2 1 0
0 CLMRF LVIRF
Reset by LVI
Held
Held
Set (1)
359