NEC 78K0/KD1 Series User Manual page 20

Figure No.
16-5 Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)......................................................................332
16-6 Format of Program Status Word................................................................................................................333
16-7 Interrupt Request Acknowledgement Processing Algorithm......................................................................335
16-8 Interrupt Request Acknowledgement Timing (Minimum Time) ..................................................................336
16-9 Interrupt Request Acknowledgement Timing (Maximum Time) .................................................................336
16-10 Examples of Multiple Interrupt Servicing ...................................................................................................338
16-11 Interrupt Request Hold ..............................................................................................................................340
17-1 Block Diagram of Key Interrupt..................................................................................................................341
17-2 Format of Key Return Mode Register (KRM).............................................................................................342
18-1 Operation Timing When STOP Mode Is Released ....................................................................................344
18-2 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ................................................345
18-3 Format of Oscillation Stabilization Time Select Register (OSTS) ..............................................................346
18-4 HALT Mode Release by Interrupt Request Generation .............................................................................349
18-5 HALT Mode Release by RESET Input.......................................................................................................350
18-6 STOP Mode Release by Interrupt Request Generation.............................................................................352
18-7 STOP Mode Release by RESET Input ......................................................................................................353
19-1 Block Diagram of Reset Function ..............................................................................................................355
19-2 Timing of Reset by RESET Input...............................................................................................................356
19-3 Timing of Reset Due to Watchdog Timer Overflow ...................................................................................356
19-4 Timing of Reset in STOP Mode by RESET Input ......................................................................................356
19-5 Format of Reset Control Flag Register (RESF) .........................................................................................359
20-1 Block Diagram of Clock Monitor ................................................................................................................360
20-2 Format of Clock Monitor Mode Register (CLM) .........................................................................................361
20-3 Timing of Clock Monitor.............................................................................................................................363
21-1 Block Diagram of Power-on-Clear Circuit ..................................................................................................367
21-2 Timing of Internal Reset Signal Generation in Power-on-Clear Circuit ......................................................367
21-3 Example of Software Processing After Release of Reset..........................................................................368
22-1 Block Diagram of Low-Voltage Detector....................................................................................................370
22-2 Format of Low-Voltage Detection Register (LVIM) ....................................................................................372
22-3 Format of Low-Voltage Detection Level Selection Register (LVIS) ...........................................................373
22-4 Timing of Low-Voltage Detector Internal Reset Signal Generation ...........................................................375
22-5 Timing of Low-Voltage Detector Interrupt Signal Generation ....................................................................377
22-6 Example of Software Processing After Release of Reset..........................................................................379
22-7 Example of Software Processing of LVI Interrupt ......................................................................................381
23-1 Block Diagram of Regulator Periphery ......................................................................................................382
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LIST OF FIGURES (6/7)
Title
Preliminary User's Manual U16315EJ1V0UD
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