NEC 78K0/KD1 Series User Manual page 403

Instruction
Mnemonic
Group
Call/return CALL !addr16
CALLF !addr11
CALLT [addr5]
BRK
RET
RETI
RETB
Stack PUSH PSW
manipulate
rp
POP PSW
rp
MOVW SP, #word
SP, AX
AX, SP
Unconditional BR !addr16
branch
$addr16
AX
Conditional BC $addr16
branch
BNC $addr16
BZ $addr16
BNZ $addr16
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 26 INSTRUCTION SET
Clocks
Operands Bytes
Note 1
3 7
2 5
1 6
1 6
1 6
1 6
1 6
1 2
1 4
1 2
1 4
−
4
−
2
−
2
6
3
6
2
8
2
6
2
6
2
6
2
6
2
Preliminary User's Manual U16315EJ1V0UD
Operation
Note 2
− (SP − 1) ← (PC + 3)
H
PC ← addr16, SP ← SP − 2
− (SP − 1) ← (PC + 2)
H
← 00001, PC
PC
15 − 11
SP ← SP − 2
− (SP − 1) ← (PC + 1)
H
← (00000000, addr5 + 1),
PC
H
← (00000000, addr5),
PC
L
SP ← SP − 2
−
(SP − 1) ← PSW, (SP − 2) ← (PC + 1)
(SP − 3) ← (PC + 1)
, PC
L
← (003EH), SP ← SP − 3, IE ← 0
PC
L
−
← (SP + 1), PC
PC
H L
SP ← SP + 2
−
← (SP + 1), PC
PC
H L
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
−
← (SP + 1), PC
PC
H L
PSW ← (SP + 2), SP ← SP + 3
−
(SP − 1) ← PSW, SP ← SP − 1
− (SP − 1) ← rp , (SP − 2) ← rp
H
SP ← SP − 2
−
PSW ← (SP), SP ← SP + 1
−
← (SP + 1), rp ← (SP),
rp
H L
SP ← SP + 2
SP ← word
10
SP ← AX
8
AX ← SP
8
−
PC ← addr16
−
PC ← PC + 2 + jdisp8
−
← A, PC ← X
PC
H L
−
PC ← PC + 2 + jdisp8 if CY = 1
−
PC ← PC + 2 + jdisp8 if CY = 0
−
PC ← PC + 2 + jdisp8 if Z = 1
−
PC ← PC + 2 + jdisp8 if Z = 0
) selected by the processor clock
CPU
Flag
Z AC CY
, (SP − 2) ← (PC + 3)
,
L
, (SP − 2) ← (PC + 2)
,
L
← addr11,
10 − 0
, (SP − 2) ← (PC + 1)
,
L
,
H
← (003FH),
H
← (SP),
← (SP),
R R R
← (SP),
R R R
,
L
R R R
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